Microprocessors which use random access memories (RAMs) for temporary storage of data typically write the data into the memory during a first clock cycle and then read the data from the memory one or more clock cycles later. However, a problem arises when a program requests data during the same cycle in which the requested data is being stored in the RAM. Since there is no way to ensure that the requested data has been completely written into the RAM at the time of the request, simultaneous reading and writing of data ordinarily is not possible.
To avoid the foregoing problem, known systems compare the address of the requested data with the write address being applied to the RAM to see if the addresses are the same. If the addresses match, then bypass gates are used to route the data directly from the input to the output of the RAM. Unfortunately, the hardware needed to implement the comparison and bypass functions require several levels of logic and is typically very complex and expensive. For example, assume a memory has two read ports and three write ports. Each time a read address is applied to one of the read ports, the read address is compared with up to three write addresses (depending upon the number of write addresses being applied to the write ports). Thus, hardware for a total of 2.times.3=6 address comparisons must be provided with the RAM chip. Additionally, if a read address matches a write address, then the data at the write port must be routed to the corresponding read port. This requires 2.times.3=6 bypass paths. If the data stored in each memory location is 64 bits long, then a total of 6.times.64 384 bypass paths are required. The complexity of the circuitry and added hardware (which consumes an inordinate amount of chip area) makes bypass techniques undesirable in many applications.